1. Field of the Invention
The present invention relates to a logic circuit portion, and the floating gate of a memory cell portion are formed in the same step and made of the same material.
2. Description of the Related Art
In a conventional logic semiconductor device having a non-volatile memory, the gate of a logic circuit portion, and the floating gate of a memory cell portion are formed in the same step and made of the same material.
For example, when the floating gate of the memory cell portion and the gate of the logic circuit portion are formed on a polysilicon layer formed in the same step as these gates, an impurity for controlling threshold values of the memory cell portion and the logic circuit portion must be doped in both the channel regions of the memory cell portion and the logic circuit portion before the polysilicon layer is formed during the manufacture.
In the above step, an annealing process for forming a second gate oxide film (inter poly) between the floating and control gates is performed in order to isolate the floating gate of the memory cell portion from the control gate after an impurity doping process and a polysilicon layer formation process. For this reason, the heat of the annealing process affects the impurity for controlling the threshold value doped in the channel region of the logic circuit portion. Thus, when the impurity for controlling the threshold value doped in the channel region of the logic circuit portion is affected by heat generated in the annealing process during formation of the second gate oxide film (inter poly) of the memory cell portion, a channel profile in the logic circuit portion is disturbed. The threshold value of the logic circuit portion is hard to control, and formation of a desired channel profile is difficult. That is, in a conventional logic semiconductor device having a non-volatile memory in which the gate of a logic circuit portion and the floating gate of the memory cell portion are made of the same material, a channel profile in the logic circuit portion is disturbed. The logic circuit portion is not suitable for micropatterning. In addition, in a conventional device, the floating gate of a memory cell portion, and the gate of the logic circuit portion are respectively made of polysilicon layers formed in the same step. For this reason, in a conventional logic semiconductor device having a non-volatile memory, in order to provide a thicknesses difference and characteristics difference between both the gate electrodes in the memory cell portion and the logic circuit portion, a photoresist film must be formed on either of the gate oxide films. Therefore, reliability of the device may be degraded, e.g., a gate breakdown voltage is decreased.